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260 lines
8.4 KiB
260 lines
8.4 KiB
#define DT_DRV_COMPAT cirque_pinnacle |
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#include <drivers/spi.h> |
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#include <init.h> |
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#include <drivers/sensor.h> |
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#include <zmk/sensors.h> |
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#include <logging/log.h> |
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#include "cirque_trackpad.h" |
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LOG_MODULE_REGISTER(pinnacle, CONFIG_SENSOR_LOG_LEVEL); |
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static int pinnacle_seq_read(const struct device *dev, const uint8_t start, uint8_t *buf, const uint8_t len) { |
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uint8_t tx_buffer[len + 3], rx_dummy[3]; |
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tx_buffer[0] = PINNACLE_READ | start; |
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memset(&tx_buffer[1], PINNACLE_AUTOINC, len + 1); |
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tx_buffer[len + 2] = PINNACLE_DUMMY; |
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const struct spi_buf tx_buf = { |
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.buf = tx_buffer, |
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.len = len + 3, |
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}; |
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const struct spi_buf_set tx = { |
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.buffers = &tx_buf, |
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.count = 1, |
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}; |
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struct spi_buf rx_buf[2] = { |
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{ |
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.buf = rx_dummy, |
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.len = 3, |
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}, |
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{ |
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.buf = buf, |
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.len = len, |
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}, |
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}; |
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const struct spi_buf_set rx = { |
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.buffers = rx_buf, |
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.count = 2, |
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}; |
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const struct pinnacle_data *data = dev->data; |
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const struct pinnacle_config *config = dev->config; |
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return spi_transceive(data->spi, &config->spi_config, &tx, &rx); |
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} |
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static int pinnacle_write(const struct device *dev, const uint8_t addr, const uint8_t val) { |
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uint8_t tx_buffer[2] = { PINNACLE_WRITE | addr, val }; |
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uint8_t rx_buffer[2]; |
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const struct spi_buf tx_buf = { |
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.buf = tx_buffer, |
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.len = 2, |
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}; |
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const struct spi_buf_set tx = { |
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.buffers = &tx_buf, |
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.count = 1, |
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}; |
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const struct spi_buf rx_buf[1] = { |
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{ |
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.buf = rx_buffer, |
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.len = sizeof(rx_buffer), |
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}, |
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}; |
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const struct spi_buf_set rx = { |
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.buffers = rx_buf, |
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.count = 1, |
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}; |
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const struct pinnacle_data *data = dev->data; |
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const struct pinnacle_config *config = dev->config; |
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const int ret = spi_transceive(data->spi, &config->spi_config, &tx, &rx); |
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if (rx_buffer[1] != 0xFB) { |
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LOG_ERR("bad ret val"); |
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return -EIO; |
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} |
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if (ret < 0) { |
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LOG_ERR("spi ret: %d", ret); |
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} |
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return ret; |
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} |
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static int pinnacle_channel_get(const struct device *dev, enum sensor_channel chan, struct sensor_value *val) { |
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const struct pinnacle_data *data = dev->data; |
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switch (chan) { |
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case SENSOR_CHAN_POS_DX: val->val1 = data->dx; break; |
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case SENSOR_CHAN_POS_DY: val->val1 = data->dy; break; |
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case SENSOR_CHAN_PRESS: val->val1 = data->btn; break; |
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default: return -ENOTSUP; |
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} |
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return 0; |
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} |
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static int pinnacle_attr_set(const struct device *dev, enum sensor_channel chan, enum sensor_attribute attr, const struct sensor_value *val) { |
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const struct pinnacle_config *config = dev->config; |
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if (attr == SENSOR_ATTR_PINNACLE_GE) { |
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const uint8_t ge_set = val->val1 ? 0 : PINNACLE_FEED_CFG2_DIS_GE; |
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const uint8_t taps_set = config->no_taps ? PINNACLE_FEED_CFG2_DIS_TAP : 0; |
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pinnacle_write(dev, PINNACLE_FEED_CFG2, ge_set | taps_set); |
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return 0; |
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} |
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return -ENOTSUP; |
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} |
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static int pinnacle_sample_fetch(const struct device *dev, enum sensor_channel chan) { |
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uint8_t packet[3]; |
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int res = pinnacle_seq_read(dev, PINNACLE_2_2_PACKET0, packet, 3); |
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if (res < 0) { |
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LOG_ERR("res: %d", res); |
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return res; |
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} |
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struct pinnacle_data *data = dev->data; |
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data->btn = packet[0] & PINNACLE_PACKET0_BTN_PRIM; |
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data->dx = (int16_t) (int8_t) packet[1]; |
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data->dy = (int16_t) (int8_t) packet[2]; |
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return 0; |
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} |
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#ifdef CONFIG_PINNACLE_TRIGGER |
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static void set_int(const struct device *dev, const bool en) { |
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const struct pinnacle_config *config = dev->config; |
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int ret = gpio_pin_interrupt_configure(config->dr_port, config->dr_pin, en ? GPIO_INT_LEVEL_ACTIVE : GPIO_INT_DISABLE); |
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if (ret < 0) { |
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LOG_ERR("can't set interrupt"); |
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} |
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} |
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static int pinnacle_trigger_set(const struct device *dev, const struct sensor_trigger *trig, sensor_trigger_handler_t handler) { |
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struct pinnacle_data *data = dev->data; |
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set_int(dev, false); |
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if (trig->type != SENSOR_TRIG_DATA_READY) { |
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return -ENOTSUP; |
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} |
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data->data_ready_trigger = trig; |
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data->data_ready_handler = handler; |
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set_int(dev, true); |
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return 0; |
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} |
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static void pinnacle_int_cb(const struct device *dev) { |
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struct pinnacle_data *data = dev->data; |
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data->data_ready_handler(dev, data->data_ready_trigger); |
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set_int(dev, true); |
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} |
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#ifdef CONFIG_PINNACLE_TRIGGER_OWN_THREAD |
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static void pinnacle_thread(void *arg) { |
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const struct device *dev = arg; |
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struct pinnacle_data *data = dev->data; |
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while (1) { |
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k_sem_take(&data->gpio_sem, K_FOREVER); |
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pinnacle_int_cb(dev); |
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pinnacle_write(dev, PINNACLE_STATUS1, 0); // Clear SW_DR |
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} |
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} |
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#elif defined(CONFIG_PINNACLE_TRIGGER_GLOBAL_THREAD) |
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static void pinnacle_work_cb(struct k_work *work) { |
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struct pinnacle_data *data = CONTAINER_OF(work, struct pinnacle_data, work); |
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pinnacle_int_cb(data->dev); |
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pinnacle_write(dev, PINNACLE_STATUS1, 0); // Clear SW_DR |
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} |
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#endif |
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static void pinnacle_gpio_cb(const struct device *port, struct gpio_callback *cb, uint32_t pins) { |
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struct pinnacle_data *data = CONTAINER_OF(cb, struct pinnacle_data, gpio_cb); |
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const struct device *dev = data->dev; |
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#if defined(CONFIG_PINNACLE_TRIGGER_OWN_THREAD) |
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k_sem_give(&data->gpio_sem); |
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#elif defined(CONFIG_PINNACLE_TRIGGER_GLOBAL_THREAD) |
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k_work_submit(&data->work); |
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#endif |
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} |
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#endif |
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#define SPI_BUS DT_BUS(DT_DRV_INST(0)) |
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#define SPI_REG DT_REG_ADDR(DT_DRV_INST(0)) |
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static int pinnacle_init(const struct device *dev) { |
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struct pinnacle_data *data = dev->data; |
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const struct pinnacle_config *config = dev->config; |
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data->spi = DEVICE_DT_GET(SPI_BUS); |
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pinnacle_write(dev, PINNACLE_STATUS1, 0); // Clear CC |
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pinnacle_write(dev, PINNACLE_Z_IDLE, 0); // No Z-Idle packets |
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if (config->sleep_en) { |
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pinnacle_write(dev, PINNACLE_SYS_CFG, PINNACLE_SYS_CFG_EN_SLEEP); |
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} |
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if (config->no_taps) { |
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pinnacle_write(dev, PINNACLE_FEED_CFG2, PINNACLE_FEED_CFG2_DIS_TAP); |
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} |
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uint8_t feed_cfg1 = PINNACLE_FEED_CFG1_EN_FEED; |
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if (config->invert_x) { |
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feed_cfg1 |= PINNACLE_FEED_CFG1_INV_X; |
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} |
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if (config->invert_y) { |
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feed_cfg1 |= PINNACLE_FEED_CFG1_INV_Y; |
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} |
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if (feed_cfg1) { |
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pinnacle_write(dev, PINNACLE_FEED_CFG1, feed_cfg1); |
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} |
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#ifdef CONFIG_PINNACLE_TRIGGER |
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data->dev = dev; |
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gpio_pin_configure(config->dr_port, config->dr_pin, GPIO_INPUT | config->dr_flags); |
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gpio_init_callback(&data->gpio_cb, pinnacle_gpio_cb, BIT(config->dr_pin)); |
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int ret = gpio_add_callback(config->dr_port, &data->gpio_cb); |
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if (ret < 0) { |
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LOG_ERR("Failed to set DR callback: %d", ret); |
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return -EIO; |
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} |
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#if defined(CONFIG_PINNACLE_TRIGGER_OWN_THREAD) |
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k_sem_init(&data->gpio_sem, 0, UINT_MAX); |
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k_thread_create(&data->thread, data->thread_stack, CONFIG_PINNACLE_THREAD_STACK_SIZE, |
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(k_thread_entry_t) pinnacle_thread, (void *) dev, 0, NULL, |
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K_PRIO_COOP(CONFIG_PINNACLE_THREAD_PRIORITY), 0, K_NO_WAIT); |
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#elif defined(CONFIG_PINNACLE_TRIGGER_GLOBAL_THREAD) |
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k_work_init(&data->work, pinnacle_work_cb); |
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#endif |
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pinnacle_write(dev, PINNACLE_FEED_CFG1, feed_cfg1); |
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#endif |
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return 0; |
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} |
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static const struct sensor_driver_api pinnacle_driver_api = { |
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#if CONFIG_PINNACLE_TRIGGER |
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.trigger_set = pinnacle_trigger_set, |
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#endif |
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.sample_fetch = pinnacle_sample_fetch, |
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.channel_get = pinnacle_channel_get, |
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.attr_set = pinnacle_attr_set, |
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}; |
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static struct pinnacle_data pinnacle_data; |
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static const struct pinnacle_config pinnacle_config = { |
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.spi_cs = { |
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.gpio_dev = DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(SPI_BUS, cs_gpios, SPI_REG)), |
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.gpio_pin = DT_GPIO_PIN_BY_IDX(SPI_BUS, cs_gpios, SPI_REG), |
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.delay = 0, |
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.gpio_dt_flags = DT_GPIO_FLAGS_BY_IDX(SPI_BUS, cs_gpios, SPI_REG), |
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}, |
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.spi_config = { |
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.cs = &pinnacle_config.spi_cs, |
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.frequency = DT_INST_PROP(0, spi_max_frequency), |
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.slave = DT_INST_REG_ADDR(0), |
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.operation = (SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_LINES_SINGLE | SPI_TRANSFER_MSB), |
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}, |
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.invert_x = DT_INST_PROP(0, invert_x), |
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.invert_y = DT_INST_PROP(0, invert_y), |
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.sleep_en = DT_INST_PROP(0, sleep), |
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.no_taps = DT_INST_PROP(0, no_taps), |
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#ifdef CONFIG_PINNACLE_TRIGGER |
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.dr_port = DEVICE_DT_GET(DT_GPIO_CTLR(DT_DRV_INST(0), dr_gpios)), |
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.dr_pin = DT_INST_GPIO_PIN(0, dr_gpios), |
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.dr_flags = DT_INST_GPIO_FLAGS(0, dr_gpios), |
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#endif |
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}; |
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DEVICE_DT_INST_DEFINE(0, pinnacle_init, device_pm_control_nop, &pinnacle_data, &pinnacle_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &pinnacle_driver_api);
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