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81 lines
3.3 KiB
81 lines
3.3 KiB
3 years ago
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#pragma once
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#include <device.h>
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#define PINNACLE_READ 0xA0
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#define PINNACLE_WRITE 0x80
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#define PINNACLE_AUTOINC 0xFC
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#define PINNACLE_DUMMY 0xFB
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// Registers
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#define PINNACLE_FW_ID 0x00 // ASIC ID.
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#define PINNACLE_FW_VER 0x01 // Firmware Version Firmware revision number.
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#define PINNACLE_STATUS1 0x02 // Contains status flags about the state of Pinnacle.
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#define PINNACLE_SYS_CFG 0x03 // Contains system operation and configuration bits.
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#define PINNACLE_SYS_CFG_EN_SLEEP BIT(2)
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#define PINNACLE_SYS_CFG_SHUTDOWN BIT(1)
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#define PINNACLE_SYS_CFG_RESET BIT(0)
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#define PINNACLE_FEED_CFG1 0x04 // Contains feed operation and configuration bits.
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#define PINNACLE_FEED_CFG1_EN_FEED BIT(0)
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#define PINNACLE_FEED_CFG1_ABS_MODE BIT(1)
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#define PINNACLE_FEED_CFG1_DIS_FILT BIT(2)
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#define PINNACLE_FEED_CFG1_DIS_X BIT(3)
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#define PINNACLE_FEED_CFG1_DIS_Y BIT(4)
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#define PINNACLE_FEED_CFG1_INV_X BIT(6)
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#define PINNACLE_FEED_CFG1_INV_Y BIT(7)
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#define PINNACLE_FEED_CFG2 0x05 // Contains feed operation and configuration bits.
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#define PINNACLE_FEED_CFG2_EN_IM BIT(0) // Intellimouse
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#define PINNACLE_FEED_CFG2_DIS_TAP BIT(1) // Disable all taps
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#define PINNACLE_FEED_CFG2_DIS_SEC BIT(2) // Disable secondary tap
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#define PINNACLE_FEED_CFG2_DIS_SCRL BIT(3) // Disable scroll
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#define PINNACLE_FEED_CFG2_DIS_GE BIT(4) // Disable GlideExtend
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#define PINNACLE_FEED_CFG2_SWAP_XY BIT(7) // Swap X & Y
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#define PINNACLE_CAL_CFG 0x07 // Contains calibration configuration bits.
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#define PINNACLE_PS2_AUX 0x08 // Contains Data register for PS/2 Aux Control.
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#define PINNACLE_SAMPLE 0x09 // Sample Rate Number of samples generated per second.
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#define PINNACLE_Z_IDLE 0x0A // Number of Z=0 packets sent when Z goes from >0 to 0.
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#define PINNACLE_Z_SCALER 0x0B // Contains the pen Z_On threshold.
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#define PINNACLE_SLEEP_INTERVAL 0x0C // Sleep Interval
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#define PINNACLE_SLEEP_TIMER 0x0D // Sleep Timer
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#define PINNACLE_AG_PACKET0 0x10 // trackpad Data (Pinnacle AG)
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#define PINNACLE_2_2_PACKET0 0x12 // trackpad Data
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#define PINNACLE_REG_COUNT 0x18
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#define PINNACLE_PACKET0_BTN_PRIM BIT(0) // Primary button
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#define PINNACLE_PACKET0_BTN_SEC BIT(1) // Secondary button
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#define PINNACLE_PACKET0_BTN_AUX BIT(2) // Auxiliary (middle?) button
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#define PINNACLE_PACKET0_X_SIGN BIT(4) // X delta sign
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#define PINNACLE_PACKET0_Y_SIGN BIT(5) // Y delta sign
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struct pinnacle_data {
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const struct device *spi;
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int16_t dx, dy;
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int8_t wheel;
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uint8_t btn;
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#ifdef CONFIG_PINNACLE_TRIGGER
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const struct device *dev;
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const struct sensor_trigger *data_ready_trigger;
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struct gpio_callback gpio_cb;
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sensor_trigger_handler_t data_ready_handler;
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#if defined(CONFIG_PINNACLE_TRIGGER_OWN_THREAD)
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K_THREAD_STACK_MEMBER(thread_stack, CONFIG_PINNACLE_THREAD_STACK_SIZE);
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struct k_sem gpio_sem;
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struct k_thread thread;
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#elif defined(CONFIG_PINNACLE_TRIGGER_GLOBAL_THREAD)
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struct k_work work;
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#endif
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#endif
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};
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struct pinnacle_config {
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struct spi_cs_control spi_cs;
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struct spi_config spi_config;
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bool invert_x, invert_y, sleep_en, no_taps;
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#ifdef CONFIG_PINNACLE_TRIGGER
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const struct device *dr_port;
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uint8_t dr_pin, dr_flags;
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#endif
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};
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